Assignment 0: 16-bit Absolute Value

Absolute value of a 16-bit 2's-complement value is not a very complex arithmetic operation. Here's a little chunk of Verilog code that computes all possible values:

module demoabs;
reg signed [15:0] a, b;
initial begin
  a = -32768;
  repeat (65536) begin
    b = ((a < 0) ? -a : a);
    $display("abs(%x) = %x", a, b);
    #1 a = a + 1;
  end
end
endmodule

The real work is just b = ((a < 0) ? -a : a);. The catch is that in this project, I want you to design a synthesizable, purely combinatorial, circuit for a 16-bit 2's complement absolute value without using Verilog word-level operators like < for less than comparison or - for negation. You also must exhaustively test your design.

So, let's talk about absolute value. There are sneaky ways, such as those documented here, to compute absolute value without a conditional comparison and branch. Of course, that doesn't really help much here because you're not allowed to use the Verilog - nor + operators in making your combinatorial circuit. It is worth noting that I would allow you to use >> (shift) and ^ (XOR) because they are bitwise operators, not really word-level arithmetic operations.

The basic point is, it's up to you what algorithm you use... and that choice will determine what other modules you might need to create as helpers.

One last point: demoabs, and any absolute value you create, will get one one value "wrong." Huh? Well, what is the absolute value of -32768 (aka, hexadecimal 8000)? The answer, of course, is 32768 -- but that value isn't representable in a 16-bit signed integer. Don't worry about that. All the methods will generate the same mathematically-wrong-but-we'll-call-it-right answer: abs(-32678) is -32678.

Your Project

Your project is about writing a Verilog module called abs, but there are actually two other chunks of Verilog code you need in order to test it. The three required modules of Verilog code are:

1. The definition of a module that starts with module refabs(b, a); and makes b the 16-bit result of taking the absolute value of a. This module MUST use at least one of Verilog's word-level operators that you're not allowed to use in your synthesizable design. Use as straightforward an implementation as possible, perhaps derived from the algorithm used in demoabs above. This refabs module will serve as your oracle to deliver known correct answers.
2. The definition of a module that starts with module abs(b, a); and makes b get the absolute value of a, but is fully synthesizable and uses only bitwise or gate-level operations. Of course, it may instantiate other combinatorial logic modules to implement its functionality, e.g., you might start with defining a 16-bit negation circuit and then instantiate that in your abs. Alternatively, you might begin by building a one-bit full adder and then a 16-bit ripple cary adder from that. You have a free choice of algorithm for how you implement abs. However, this module MUST be Verilog code that you author using synthesizable, purely combinatorial, logic -- it is NOT permitted to use word-level Verilog operators (as noted above) in itself nor in anything it instantiates.
3. The definition of a non-synthesizable module that starts with module testbench; and instantiates a abs which it exhaustively tests for correctness. Note that it is not sufficient to just print what happens for all 65,536 possible input values; I don't want just a stimulus module. Who would want to manually check 65,536 lines of output? Your testbench must not only try each possible input value, but also must check that the answer from your abs matches the answer from refabs in each case. Your testbench should only output the combinations of inputs for which the answer from abs was wrong. Further, it should count how many input combinations were correct and how many failed. The last line of text output should be generated by Verilog code like:

   $display("All cases tested; %d correct, %d failed", correct, failed);
   

Place all your verilog code for the above in one file called abs.v. That's the file you need to submit.

Naturally, I also expect you to run that file through a Verilog compiler either using our CGI interface or Icarus Verilog directly:

iverilog -o abs abs.v

And to run the simulation to test it:

vvp abs

Which will hopefully result in it printing just:

All cases tested; 65536 correct, 0 failed

If not, and you can't figure-out how to fix it, as Ricky Ricardo would say, you got some splainin to do. ;-)

Details For The Implementor's Notes

You should be submitting an implementor's notes document with your project. Just a couple of quick comments about that....

Your implementor's notes certainly should describe the logic used to implement your abs module. That can be done as text. I am not requiring you to provide a schematic of your abs module... it's rather simple and the schematic wouldn't really be very useful. However, practice creating schematics is certainly a good thing (i.e., a skill you will appreciate in this course) and it wouldn't hurt to include a schematic.

Although I would encourage you to think about generating a VCD file and using gtkwave to visualize it, I don't think there's much point in doing that for a simple combinatorial circuit like abs. If you do find it useful, you may include a screen grab from gtkwave in your implementor's notes.

Due Dates

The recommended due date for this assignment is before class, Monday, February 4, 2019. This submission window will close when class begins on Wednesday, February 6, 2019. You may submit as many times as you wish, but only the last submission that you make before class begins on Wednesday, February 6, 2019 will be counted toward your course grade.

Note that you can ensure that you get at least half credit for this project by simply submitting a tar of an "implementor's notes" document explaining that your project doesn't work because you have not done it yet. Given that, perhaps you should start by immediately making and submitting your implementor's notes document? (I would!)

Submission Procedure

For each project, you will be submitting a tarball (i.e., a file with the name ending in .tar or .tgz) that contains all things relevant to your work on the project. Minimally, each project tarball includes the source code for the project and a semi-formal "implementors notes" document as a PDF named notes.pdf. It also may include test cases, sample output, a make file, etc., but should not include any files that are built by your Makefile (e.g., no binary executables). For this particular project, name the Verilog source file abs.v.

Submit your tarball below. The file can be either an ordinary .tar file created using tar cvf file.tar yourprojectfiles or a compressed .tgz file file created using tar zcvf file.tgz yourprojectfiles. Be careful about using * as a shorthand in listing yourprojectfiles on the command line, because if the output tar file is listed in the expansion, the result can be an infinite file (which is not ok).