Spring 2019 EE380 Assignment 5

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1. For this question, check all that apply. Consider the following two MIPS subset implementations:
   
   
   Which of the following statements about how pipelining changes the architecture is true?
   The Data Memory module could be the same circuit in both implementations
   The Instruction Memory module could be the same circuit in both implementations
   The ALU used to add 4 to the PC could be the same circuit in both implementations
   The ALU used for operations like add and xor could be the same circuit in both implementations
2. Suppose that a single-cycle design can execute with a clock cycle of 500ns. When broken into a 5-stage pipeline, the delays for each of the stages are 100ns, 50ns, 200ns, 100ns, and 50ns. Approximately what clock rate would you expect the pipelined version to run at and what speedup would that give over the single-cycle design?
   
3. For this question, check all that apply. Consider executing each of the following code sequences on the pipelined MIPS implementation given below:
   
   Which of the following statements best describes the execution times you would expect to observe?
   

   (A)  addi $t1,$t0,4
        lw   $t2,0($t1)
        xor  $t2,$t2,$t3
   
   (B)  addi $t1,$t0,4
        lw   $t2,0($t0)
        xor  $t4,$t0,$t3
   

   
   (A) would be sped up if we used value forwarding
   (B) would be sped up if we used value forwarding
   (A) would be faster than (B) without value forwarding
   (B) would be faster than (A) without value forwarding
4. Consider executing each of the following code sequences on the pipelined MIPS implementation given below:
   
   Reorder the following code so that it completes in fewer clock cycles and explain what you did. You should assume the that the processor does not implement value forwarding.
   

   sub  $t2,$t1,$t0
   add  $t3,$t2,$t0
   ori  $t4,$t4,42
   lw   $t2,0($t0)
   

   
   
5. Briefly explain the difference between a BHB and a BTB.
   

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