Spring 2019 EE380 Assignment 1 Sample Solution

  1. For this question, check all that apply. Which of the following statements is/are true?
    Allowing a few simultaneous readers from a bus is easy
    SRAM usually takes less power per bit held than DRAM
    A multiplexor can be built using a decoder and tri-state drivers
    The MFC signal indicates that the most recent memory fetch request completed
    Zin only makes sense in a state where the ALU is doing something (e.g., ALUadd)
  2. For this question, check all that apply. Here's something you know from EE280: Which of the following logic equations implement a multiplexor with two inputs, i0 and i1, and one select line, s?
    ((s OR (NOT i0)) AND (s OR i1))
    ((i1 AND (NOT s)) OR (i0 AND s))
    ((i1 AND s) OR (i0 AND (NOT s)))
    ((s AND (NOT i1)) OR (s AND i0))
    (((NOT s) AND i0) OR (s AND i1))
  3. Given this processor hardware design, add control states to the following to implement an OR-with-immediate instruction (as decoded by the when below), such that ori $rt,$rs,immed yields rt=(rs|immed). This is actually a MIPS instruction, as we'll discuss later. Hint: it's a lot like the addi given to you, isn't it? You should add initial values and test your design using the simulator before submitting it here.

    You can test your code with: 

    MEM[0]={ori}+rs(9)+rt(10)+immed(10)
MEM[4]=0
$9=34

    Register $10 should end-up holding the value 0x0000002a (42 in decimal).

  4. Given this processor hardware design, add control states to the following to implement a "fortytwo" instruction (as decoded by the when below), such that fortytwo immed($rs) places the value forty-two in memory, i.e., mem[rs+immed]=42;. You should add initial values and test your design using the simulator before submitting it here.

    You can test your code with: 

    MEM[0]=op(2)+rs(1)+immed(40)
MEM[4]=0
MEM[44]=1
$1=4

    Memory MEM[44] should end-up holding the value 0x0000002a (0x2a is 42 decimal).

  5. Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy $rt,$rs. 
    when op() op(1) Xyzzy

Start:
 PCout, MARin, MEMread, Yin
 CONST(4), ALUadd, Zin, UNTILmfc
 MDRout, IRin
 Zout, PCin, JUMPonop
 HALT /* Should end here on undecoded op */

Xyzzy:
 SELrs, REGout, Yin
 CONST(-1), ALUxor, Zin
 Zout, SELrt, REGin, JUMP(Start)

  6. Given the xyzzy $rt,$rs instruction as defined above, and assuming that a memory load request takes 8 clock cycles to complete (after MEMread has been issued), how many clock cycles would it take to execute each xyzzy instruction? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here:
  7. Given this processor hardware design, suppose that the following control state is the limiting factor in determining the maximum clock speed. Given that the propagation delay associated with Zin is 1ns, MARin is 2ns, REGout is 4ns, SELrt is 8ns, and ALUslt is 16ns, what is the period (in nanoseconds) of the fastest allowable clock? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here: 
    ALUslt, Zin, SELrt, REGout, MARin

  8. Given this processor hardware design, add control states to the following to implement a multiply-by-4 instruction (as decoded by the when below), such that mul4 rd makes rd=4*rd;. Note that there is no multiplier per se in the ALU. You should add initial values and test your design using the simulator before submitting it here.

    You can test your code with: 

    MEM[0]=op(1)+rd(8)
MEM[4]=0
$8=3

    Register $8 should end-up holding the value 0x0000000c.

  9. Given this processor hardware design, add control states to the following to implement an exchange-with-memory instruction (as decoded by the when below), such that xchg $rt,@$rs swaps the values in register rt and memory[rs]. Hint: swaps are usually done using a temporary register -- Y is a good choice. You should add initial values and test your design using the simulator before submitting it here.

    You should be able to make your own test case.... ;-)

  10. What high-level languages call goto is usually called a jump instruction in assembly language. The catch is that you can't have a 6-bit opcode and a 32-bit (immediate) memory address fit in one 32-bit instruction. MIPS handles this a little strangely, so let's make a more normal jump instruction called jmp, which takes two words. The first is the instruction with the opcode, the second is just the 32-bit jump target address. Thus, jmp 0x12345678 would be encoded as two words: 0xfc000000 and 0x12345678. Executing that instruction would make the next instruction be taken from memory address 0x12345678. Add states to the following to implement the jmp instruction.

    You can test your code with: 

    MEM[0]=op(1) /* Jmp */
MEM[4]=400   /* to address 400 */
MEM[400]=op(2)

    The simulator should stop after failing to decode the instruction fetched from MEM[400], at which time the PC should hold 404, which is 0x00000194.

EE380 Computer Organization and Design.